This invention relates in general to queued interrupt techniques in computer systems and in particular, to a technique and mechanism for controlling the queuing and subsequent reading of interrupt information in either direction between two processors.
In computer systems, an interrupted processor frequently requires additional information from an interrupting device in order to properly respond to an interrupt. For example, when the interrupted processor executes an interrupt service routine ("ISR") in response to the interrupt, the ISR first ascertains the exact kind of external event that caused the interrupt, then it performs various actions responsive to that event.
In order to minimize the number of program steps and consequently, the execution time that the ISR must spend on ascertaining what kind of event has occurred, special hardware may be implemented so that for each interrupt, the interrupted processor initiates a special kind of bus cycle called an "interrupt acknowledge cycle." In this cycle, the interrupted processor typically reads an interrupt vector generated by the interrupting device that provides certain identification information about what kind of event caused the interrupt. The processor then typically uses the interrupt vector thus obtained as an index or pointer to select a starting address for the appropriate ISR to be executed from a table of such addresses. Additional information, if necessary, can then subsequently be obtained by the selected ISR.
It is also sometimes desirable to form interrupt queues between devices, and to facilitate the organized writing and reading of interrupt information into and out of such queues by the respective interrupting and interrupted devices. For example, since the processing initiated by an interrupt may take some time, the interrupting device may again develop a need to interrupt the interrupted device for a similar or different reason or event during such interrupt processing time. In such a case, the not-yet-acted-upon interrupts are stored in a queue which the interrupted device can access and later act upon when it is free to do so.